1. Field of the Invention
The present invention relates to current mirror circuits. More particularly, the present invention relates to a current-mirror circuit including a biasing current to speed up current-mirror settling time
2. The Prior Art
Simple prior-art current-mirror circuits are shown in FIGS. 1A and 1B. The circuit of FIG. 1A transfers the input current Iin to a load circuit by two p-channel mirror-connected transistors. The current generator schematically represents any generic current source that supplies the input current to the mirror connected transistors, and the capacitance represents any possible load capacitance associated with the node connecting together the gates of the two transistors. In FIG. 1B, an equivalent circuit using two n-channel mirror-connected transistors is shown. The two circuits are equivalent from an operation point of view. By changing the ratio of the dimensions of the mirror-connected transistors dimensions ratio, the steady-state output current can be made to be greater or smaller than the input current.
Typically, two constraints may be considered as critical for a current mirror circuit: the precision with which the output current is equal to the desired value, and the speed with which it reaches the final value once the circuit is powered on. Once the circuit is powered on, Iout does not reach its desired value until all the circuit internal nodes reach their steady-state operating conditions. The time needed by currents and voltages to achieve their final value is usually referred to as voltage or current settling time. During the transient turn-on period, the node connecting together the gates of the two transistors is driven by the current sunk by the diode-connected transistor. Its behavior is shown in the current-to-voltage characteristic of FIG. 2. Once this circuit is powered on, the node connecting together the gates of the two transistors starts, for example, from GND and reaches its steady state voltage value for which IDS=Iin. Looking at the transistor characteristic, this means that the diode-connected transistor reaches its operating point A from the right (for example, from VDS=VDD).
As shown in FIG. 2, the diode-connected transistor sinks more current than Iin until its gate to source voltage (also drain to source voltage) is greater than its final value. This extra current charges node connecting together the gates of the two transistors close to its steady state voltage value, in a time depending on the dimensions (W and L) of the diode-connected transistor; the larger is it, the greater is the current supplied to the node and, thus, the shorter is the time with which its voltage value approaches to the point A. For this reason, typically, a large diode-connected transistor is chosen. Once the node voltage is about to definitively reach its final value, the transistor current diminishes together with the transistor transconductance (that is, the curve slope, shown in FIG. 2), which indicates the strength with which the diode-connected transistor drives the node up to its steady state value.
A critical situation is that in which a very low current Iin has to be supplied by a large diode-connected transistor in the steady-state condition. In such a case, the point A could be quite close to the transistor turning off condition. This means that it reaches its steady-state condition in a very slow manner, in particular, in a noticeably asymptotic manner. As a consequence, this last transient phase could take most of the total settling time.
The purpose of current-mirror circuits is to transfer, in the fastest possible way, the precise value of the current Iin to the output node. Such precision is obtained only once the operating point of the diode-connected transistor is at point A in the curve of FIG. 2. As a consequence, the entire asymptotic transient phase must be finished to obtain such a precision. It is important to emphasize that, for the reasons given above, a critical situation could occur independently of the value of the load capacitance coupled with the gate of the mirror-connected transistors even if the capacitance of the node is small. In fact, a very low current Iin supplied to a large diode-connected transistor can result a very long asymptotic behavior of the node since the operating point is close to the turn-off point of the transistor.
Thus, for the current-mirror circuits of FIGS. 1A and 1B, employing a larger diode-connected transistor speeds up the initial transient phase where the drain-to-source voltage is far from the turn-off point, but slows down the subsequent transient period where the drain-to-source voltage value is about to reach a steady-state value that is close to its turn-off point.
One way to transfer the input current to a remote load circuit is to use a chain of mirror-connected transistors like those shown in the circuit of FIG. 3A. As shown in FIG. 3A, the circuit generates a current supplied to a remote load circuit. Those of ordinary skill in the art will observe that this current-mirror chain is practically obtained merging together a p-channel and an n-channel current mirror like those shown in FIGS. 1A and 1B. To simplify the analysis, the conditions Iout=Iin and Imirr=Iin are considered. For several reasons, the current-generator portion of the circuit and the p-channel transistors and the diode-connected n-channel transistor could be at a very different chip location than that of the load circuit and the driven n-channel transistor. Accordingly, the interconnect path may generally be modeled by an RC network.
The output-current settling time could be quite long, for example, if a long interconnect path links the two sides of the circuit and a low current drives the RC network. The circuit in FIG. 3B attempts to speed up the transient circuit behavior to solve this problem by sizing the driven p-channel transistor and the diode-connected n-channel transistor to be m times larger so that the current driving the RC network is m times greater. However, sizing the driven p-channel transistor to be m times larger also makes its gate capacitance m times larger, increasing the gate voltage settling time. FIG. 4 shows the output current curves of the circuits of FIGS. 3A and 3B. As shown in FIG. 4, choosing the right value for m, results in an output current settling time for the circuit of FIG. 3B circuit that is less than the circuit of FIG. 3A.
The circuit shown in FIG. 3C is a more general version of the circuits of FIGS. 3A and 3B in which the two capacitances represent any possible load capacitance respectively on the p-channel and n-channel gate nodes. For example, the capacitances C1 and C2 could represent, respectively, the p-channel transistor gate capacitance, and the capacitance of the RC network. Depending on the value of C1 and C2, and on the current supplied to them, the circuit speed could be limited by the voltage settling time of either the C1 node or the C2 node.